This application claims priority based on Korean Patent Application No. 2003-52090, filed on Jul. 28, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Technical Field
The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a plurality of identical patterns in one plane.
2. Discussion of Related Art
Defect analysis is performed during the manufacture of semiconductor devices to provide quality control and ultimately increase yield. Defect analysis is performed using a microscope, a focused ion beam (FIB), a scanning electron microscope (SEM), or an e-beam probe. These devices are used to find a desired point with a ruler and to enlarge the point and check for defects or a desired pattern. When a defect is anticipated or found near a specific pattern, the next step is to examine the vicinity and determine the cause of the defect. However, since semiconductor devices are made up of identical structures arranged in repeating patterns, it is often very difficult to find a specific location in a semiconductor device.
Since semiconductor devices are now being formed with up to 6 or 7 layers of metal wiring stacked on top of one another, chemical mechanical polishing (CMP) technology has increased in importance. Accordingly, the practice of forming identical dummy patterns 10 on a top layer, as shown in FIG. 1, has increased. As is well-known in the art, dummy patterns are intended to reduce dishing in a CMP process by reducing differences in pattern density.
When a ruler of a test device is used to search for a desired point on a semiconductor device according to conventional methods, it is sometimes very difficult to locate the exact point if a distance to the point becomes too great. In the dummy patterns of FIG. 1, the point is located from a certain pad that is visible to the naked eye with the aid of a magnifying device (pads are usually larger than dummy patterns), or from a certain inner chip with a ruler. However, the number of dummy patterns etc. that must be counted to find a desired point on the semiconductor device naturally increases with the distance to the desired point, and there is a high probability of error when counting dozens or hundreds of dummy patterns, and checking pads and inner chips, just by looking at a screen of the test device.
In addition, if milling with an FIB is done in the wrong place, even only slightly off from the desired point, it can ruin a sample and cause a serious problem. For example, FIG. 2 shows a metal line pattern arrangement in which electrical characteristics of a first wire 20 are to be checked by milling a point A and filling it with metal. If, by mistake, a point B is milled and filled with metal, a short between the first wire 20 and a second wire 30 occurs and the sample is ruined.
Furthermore, in recently developed high-performance semiconductor devices or semiconductor devices that have high power consumption, a reference plain 50 is used to smoothly supply power to the top layer, as shown in FIG. 3. For example, the reference plain 50 is used in a high-speed central processing unit (CPU). The reference plain 50 is formed as one metal plain dotted with via holes 55 for connection to a lower layer. Here, since the via holes 55 have a uniform pattern across the reference plain 50, similar to the dummy patterns 10 of FIG. 1, it is very difficult to find an exact point that is far away from pads using a test device according to conventional methods.
Moreover, line width is constantly being reduced by ongoing improvement in techniques for manufacturing semiconductor devices. This reduction of line width makes finding exact points on semiconductor devices increasingly difficult.
Accordingly, there is a need for a semiconductor device in which a defect or a desired point can be easily located and analyzed.